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IEEE Journal of Solid-State Circuits

Publication date: 2013-01-01
Volume: 48 Pages: 91 - 103
Publisher: Institute of Electrical and Electronics Engineers

Author:

Lakdawala, H
Schaecher, M ; Fu, CT ; Limaye, R ; Duster, J ; Tan, Y ; Balankutty, A ; Alpman, E ; Lee, C ; Minh Nguyen, K ; Lee, HJ ; Ravi, A ; Suzuki, S ; Carlton, B ; Kim, HS ; Verhelst, Marian ; Pellerano, S ; Kim, T ; Venkatesan, S ; Srivastava, D ; Vandervoorn, P ; Rizk, J ; Soumyanath, Ch ; Yavatkar, R ; Ramamurthy, S

Keywords:

Science & Technology, Technology, Engineering, Electrical & Electronic, Engineering, Clock generation, CMOS low noise amplifier, CMOS power amplifier, network on chip, RF circuit design, system fabric, system on chip, 0204 Condensed Matter Physics, 0906 Electrical and Electronic Engineering, 1099 Other Technology, Electrical & Electronic Engineering, 4009 Electronics, sensors and digital hardware

Abstract:

An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of-74 dBm,-8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency. © 1966-2012 IEEE.