Design of Low-Noise Integrated Circuits for In Vivo Neural Interfaces (Design van lage-ruis geïntegreerde circuits voor in vivo neuronale interfaces)
Design of Low-Noise Integrated Circuits for In Vivo Neural Interfaces
Mora López, Carolina; S0208396
Understanding how the brain functions is a great challenge for neuroscientists. Therefore, powerful and advanced technologies are necessary to unravel the complex interactions among neurons. Since a few decades, microfabricated neural probes are being used, together with microelectronic interfaces, to get more insight in the activity of neuronal networks. The need for higher temporal and spatial recording resolutions imposes new challenges on the design of integrated neural interfaces with respect to power consumption, data handling and versatility. The primary goal of this thesis is to design and implement low-power, high-performance integrated circuits and systems for the accurate recording of in vivo neural signals.In this thesis, two different neural recording systems were implemented and validated. The first prototype implements an integrated acquisition system for in vitro and in vivo applications. The ASIC consists of 16 low-noise, fully-differential input channels with independently programmable amplification (from 100 to 6000) and filtering (1-6000 Hz range) capabilities. Each channel is AC-coupled and implements a fourth-order band-pass filter in order to steeply attenuate out-of-band noise and DC input offsets. The system achieves an input-referred noise density of 37 nV/sqrt(Hz), a NEF of 5.1, a CMRR > 60 dB, a THD > 1% and a sampling rate of 30 kS/s per channel, while consuming a maximum of 70 uA per channel from a single 3.3 V supply. The ASIC was implemented in a 0.35 um CMOS technology and has a total area of 5.6 x 4.5 mm2. The recording system was successfully validated in in vitro and in vivo experiments, achieving simultaneous multichannel recordings of cell activity with satisfactory signal-to-noise ratios.The second prototype focuses on the implementation of a full-CMOS active neural probe, which was fabricated in a 0.18 um CMOS technology. Power and area optimizations were the main targets in this implantable device. The neural probe has 455 recording electrodes and 52 recording channels. Underneath each electrode there is in situ amplification and AC coupling. The recording channels have independent programmable amplifiers and filters to process the analog signals coming from the electrodes. The probe also includes integrated ADCs and a digital serial interface (SPI) for data transferring. The design achieves an input-referred noise density of 44 nV/sqrt(Hz), a sampling rate of 30 kS/s per channel and a resolution of 10 bits, while consuming a total power of 17.7 uW per channel from a single 1.8 V supply. The body of the probe occupies an area of 2.9 x 3.2 mm2. The complete functionality of this neural probe was successfully demonstrated in in vivo experiments, achieving massive parallel recording of neural signals.In conclusion, the work presented in this thesis represents an essential step towards the design of effective high-density neural interfaces, which may serve as important tools in basic neuroscience research and as part of future neuroprosthetic devices.