Title: Design Space Exploration for Automatically Generated Cryptographic Hardware using Functional Languages
Authors: Wolfs, Davy
Aerts, Kris ×
Mentens, Nele #
Issue Date: 2012
Publisher: IEEE
Host Document: 22nd International Conference on Field Programmable Logic and Applications (FPL 2012) edition:22nd pages:671-674
Conference: FPL 2012 edition:22 location:Oslo date:August 29-31, 2012
Abstract: This paper presents an EDA (Electronic Design Automation) tool that generates basic building blocks for crypto-graphic hardware in VHDL. The purpose of the tool is to decrease the design time of cryptographic hardware and to allow designers to make abstraction of both the arithmetic
and design complexity. The tool generates multiple implementations for one arithmetic description and then benchmarks the implementations to find the most optimal, based upon design space parameters. These parameters consist of area and speed requirements. We present datapath and control logic results for a Xilinx Virtex-5 FPGA.

The novelty in our approach lies in the fact that we exploit the higher-order features of functional languages to facilitate the design space exploration and that we take benefit from the strength of the third-party synthesis tool by generating VHDL code at an abstraction level that is higher than the gate level. Nevertheless, in this stage of the development of the tool, the different cryptographic architectures are hand-made and the selection of the most optimal solution, based upon user requirements, is done by exhaustive search. This means that the tool leaves room for improvement, but forms a solid base for further development.
Publication status: published
KU Leuven publication type: IC
Appears in Collections:ESAT - STADIUS, Stadius Centre for Dynamical Systems, Signal Processing and Data Analytics
Informatics Section
Departement Industriële Wetenschappen en Technologie - UC Limburg
Technologiecluster Computerwetenschappen
Computer Science Technology TC, Technology Campus Diepenbeek
Electrical Engineering (ESAT) TC, Technology Campus Diepenbeek
Technologiecluster ESAT Elektrotechnische Engineering
× corresponding author
# (joint) last author

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