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Title: Fabrication and Characterization of Ultra-Thin Silicon Crystalline Wafers for Photovoltaic Applications using a Stress-Induced Lift-off Method (Maken en karakterizeren van ultra-dunne kristallijne silicium substraten met een spanningsgeïnduceerde kliefmethode voor fotovoltaïsche toepassingen)
Other Titles: Fabrication and Characterization of Ultra-Thin Silicon Crystalline Wafers for Photovoltaic Applications using a Stress-Induced Lift-off Method
Authors: Masolin, Alex
Issue Date: 6-Nov-2012
Abstract: In order to reduce material-related costs, there is a need to develop new wafering techniques to produce thin (< 100 µm) crystalline silicon wafers for photovoltaic applications.This work presents a new kerf-free wafering process for single crystal silicon which relies only on thermo-mechanical treatments. The process is named SLIM-Cut (Stress-Induced LIft-off Method).The process flow is as follows: a layer of a material with a coefficient of thermal expansion (metal or polymer) significantly different from silicon is deposited on top of a bare silicon substrate that could be a few centimeters thick. The system formed by the silicon substrate and the stress-inducing layer later undergoes a thermal process. Upon cooling, the stress-inducing layer will shrink more than the silicon creating a stress field inside the silicon substrate, provided that the bonding is strong enough to withstand this stress.When the stress reaches a threshold value, the system tends to relax the constraints by propagating a crack either in the stress-inducing layer itself, along the interface, or completely through the substrate (ingot). If the mechanical parameters are chosen carefully, there is a third option for the trajectory of the crack: propagating inside the silicon at a fixed distance from the interface, parallel to the surface, i.e. substrate spalling.The quality of the resulting material must be assessed to ensure that this innovative silicon foil approach does not jeopardize the potential efficiency of the final solar cell. Microwave-detected photoconductance decay, deep-level transient spectroscopy, electron spin resonance and optical inspections after defect etching of the foils surface were performed to asses wafer quality in terms of electronic activity, defect density and location.A metal-based approach for the stress inducing layer involves high-temperatures, above the transition temperature for silicon from brittle to ductile. This leads to poor foil quality due to plastic deformations of the material and possible contamination of the foil. Currently, a metal-based approach involving high temperatures is not suitable for the fabrication of PV material.Conversely, a polymer-based approach involves only low-temperature steps (max 150 ºC). The obtained foils show important roughness and thickness variations which could be reduced avoiding manual processing. Analyses of the silicon foils fabricated in this way indicate that the material quality is preserved, e.g. high bulk lifetimes and low defect densities demonstrate the suitability of the foils for high-efficiency solar cell processing.
Table of Contents: Abstract
Beknopte samenvatting
Abbreviations
Contents
List of Figures
List of Tables
1 Introduction
1.1 Rationale of the thesis
1.2 Industrial state-of-the art technology
1.3 Alternative wafering approaches
1.4 Solid phase wafering
1.5 Outline of the thesis
2 Fracture mechanics and thermo-mechanical properties of silicon
2.1 Fracture mechanics
2.1.1 Theory of brittle fracture
2.1.2 Linear Elastic Fracture Mechanics theory
2.1.3 Crack propagation criterion
2.2 Thermo-mechanical properties of silicon
2.2.1 Young’s Modulus
2.2.2 Temperature effects on elastic constants
2.2.3 Coefficient of Thermal Expansion
2.2.4 The Brittle-to-Ductile Transition Temperature
2.2.5 Fracture toughness
2.2.6 Crack speed
2.3 Steady-state crack propagation
2.3.1 Influence of the Young’s Modulus on the crack propagation
2.4 Envisaged process – SLIM-Cut
2.4.1 Choice of stress-inducing layer
2.5 Conclusions
3 SLIM-Cut process development
3.1 Process steps optimization
3.1.1 Notching
3.1.2 Screen-printing
3.1.3 Drying
3.1.4 Firing
3.1.5 Cleaning
3.2 Effect of peak temperature on the silicon foil
3.3 Conclusions
4 Investigation and characterization of the foil properties
4.1 <111> vs. <100>
4.2 Mechanical integrity and stability
4.3 Minority-carrier lifetime
4.3.1 Setting up a target for bulk minority-carrier lifetime
4.3.2 Evaluation of minority-carrier lifetime of silicon foils
4.4 Conclusions
5 An alternative low-temperature approach: polymer-based SLIM-Cut
5.1 Polymer as stress-inducing layer
5.2 Process flow
5.3 Characterization
5.3.1 Bow, TTV, roughness
5.3.2 Minority-carrier lifetime
5.3.3 Defect etching
5.3.4 Electron Spin Resonance
5.3.5 Deep Level Transient Spectroscopy
5.4 Conclusions
6 Conclusions and outlook
6.1 Outlook
A Tools & characterization techniques
A.1 Screen-printing
A.2 Zone-melting recrystallization
A.3 Optical profilometry
A.4 Deep level transient spectroscopy
A.4.1 Schottky barrier diodes
A.4.2 Deep Level Transient Spectroscopy
A.4.3 The capacitance transient and DLTS signal
A.4.4 Calculating trap energy levels and capture cross-sections
A.4.5 Calculating trap concentrations
A.5 Dam & Fill
Bibliography
List of publications
Curriculum Vitæ
ISBN: 978-94-6018-586-1
Publication status: published
KU Leuven publication type: TH
Appears in Collections:ESAT - ELECTA, Electrical Energy Computer Architectures
Electrical Engineering - miscellaneous
Associated Section of ESAT - INSYS, Integrated Systems

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