Title: Analog IC Reliability in Nanometer CMOS - Transistor Modeling and Circuit Simulation (Betrouwbaarheid van analoge geïntegreerde schakelingen in nanometer CMOS - Transistor modellering en circuit simulatie)
Other Titles: Analog IC Reliability in Nanometer CMOS - Transistor Modeling and Circuit Simulation
Authors: Maricau, Elie; S0174272
Issue Date: 25-Oct-2012
Abstract: Today, micro-electronic circuits are undeniably and ubiquitously present in our society. Transportation vehicles such as cars, trains, buses and airplanes make abundant use of electronic circuits to reduce energy consumption and emission of greenhouse gasses and to increase passenger safety and travel comfort. Other products using electronic circuits are smartphones, tablet PCs, game consoles, household appliances, satellites, base stations, servers, etc. Each of these applications is becoming increasingly more complex to build. At the same time, the quality and reliability requirements for electronic circuits are more demanding than ever.To guarantee a high production yield and a sufficient circuit lifetime, possible hazards and failure effects have to be considered throughout the entire design flow. Such a flow includes the initial concept, the design itself, the testing of the prototype circuit and finally the production process. The majority of integrated circuits manufactured today is processed in a complementary metal-oxide semiconductor (CMOS) technology. To reduce cost and to increase performance, the dimensions of all circuit components are shrinked with each new technology node. Associated with this technology scaling are the atomistic size of modern transistors, an increase of the gate-oxide electric field and the introduction of new gate and channel materials. The combination of these elements results in an emerging reliability problem for advanced nanometer CMOS technologies. Transistor wearout manifests itself as a gradual and time-dependent shift of circuit characteristics which can result in circuit failure. Especially analog circuits, which are typically used as an interface between the real world and a digital backend, can be very sensitive to such small circuit parameter variations.This PhD work focuses on the simulation and analysis of analog circuit reliability. The models and simulation techniques proposed in this dissertation are aimed to serve as an aid for circuit designers to better understand the impact of aging effects on their circuits and to enable the development of failure-resilient design solutions. In a first part of the work, an overview of all relevant nanometer CMOS unreliability effects is given and transistor compact models for the most important aging effects are proposed. A distinction between spatial unreliability effects, resulting from process variations, and temperoral unreliability effects, which are time-dependent, can be made. The latter can again be divided into transient effects such as noise and electromagnetic interference, and aging effects such as breakdown, bias temperature instability and hot carrier injection. This work primarily concentrates on the aging effects. To enable efficient and accurate circuit lifetime simulations, transistor compact models for each aging effect are proposed. These models include the most important circuit-related stress parameters such as voltages, transistor dimensions and temperature. Important effects such as partial recovery ofthetransistor damage when the stress voltage is reduced, are also supported. Each model is validated with measurements. Also, models for stochastic aging effects in sub-45nm CMOS, whichresult in time-dependent transistor mismatch, are discussed. A second part of the thesis focuses on the development of efficient simulation methods to analyze the impact of transistor aging on an entire circuit. Existing reliability simulators, published in literature or commercially available, still suffer from a lot of deficiencies. Often, these tools do not support all unreliability effects and especially the impact of process variations and stochastic aging effects is in most cases not included. The tool set presented in this work aims to solve these problems, while still limiting the computational effort. The proposed simulator includes support for all important deterministic and stochastic aging effects. Further, the interaction between process variations and aging effects can be analyzed and visualized. In addition to a visualization of the time-dependent performance shift of the circuit under test, reliability weak spots can be detected. This enables a designer to search for dedicated solutions in case of a reliability problem. To limit the simulation time, the simulator uses a response surface method which models the time-dependent circuit performance based on only a limited set of SPICE-based reliability simulations. Finally, a hierarchical simulation framework based on an adaptive sample selection algorithm and a non-linear symbolic regression algorithm enables the reliability simulation of large analog circuits within a reasonable time frame. Each part of the simulation framework is demonstrated on an example circuit. The last part of this work applies the proposed reliability compact models and simulation methods to a set of commonly used analog circuits. Factors that determine the circuit lifetime are explored and illustrated with examples. Further, a design for reliability flow is demonstrated on an example IDAC circuit resulting in the design of a reliable circuit with minimum guardbanding. Finally, the lifetime of small- to medium-sized digital circuits is investigated. Although the methods proposed in this work are primarily intended for analog circuits, they are also applicable to small- and medium-sized digital circuits when these are defined as a SPICE netlist. The models and simulation techniques developed in this work are intended as a first step towards understanding the impact of transistor aging on analog integrated circuits. Eventually, this understanding can help designers in designing guaranteed reliable and robust circuits in future CMOS process nodes.
Table of Contents: Voorwoord
List of Abbreviations and Symbols
List of Figures
List of Tables
1 Introduction
1.1 Introduction
1.2 Reliability Engineering: a Brief History
1.3 Reliability of Electronic Systems
1.4 Reliability in Nanometer CMOS
1.4.1 Reduction of the Effective Oxide Thickness
1.4.2 Introduction of New Materials and Devices
1.4.3 Atomic-Scale Dimensions
1.4.4 Mission Profiles
1.4.5 Time and Money Constraints
1.5 Design for Reliability
1.5.1 Define
1.5.2 Identify
1.5.3 Analyze and Assess
1.5.4 Quantify, Improve and Validate
1.5.5 Monitor and Control
1.6 Thesis Motivation and Outline
1.7 Conclusions
2 CMOS Reliability Overview
2.1 Introduction
2.2 The Origin of CMOS Unreliability
2.3 Spatial Unreliability
2.3.1 Systematic Effects
2.3.2 Random Effects
2.4 Temporal Unreliability
2.4.1 Aging Effects
2.4.2 Transient Effects
2.5 Conclusions
3 Transistor Aging Compact Modeling
3.1 Introduction
3.2 Hot Carrier Injection
3.2.1 Background
3.2.2 A HCI Compact Model for Circuit Simulation
3.2.3 HCI in sub-45nm CMOS
3.3 Bias Temperature Instability
3.3.1 Background
3.3.2 A BTI Compact Model for Circuit Simulation
3.3.3 Model Calibration and Validation
3.3.4 BTI in Sub-45nm CMOS
3.4 Time-Dependent Dielectric Breakdown
3.4.1 Hard Breakdown
3.4.2 Soft Breakdown
3.5 Aging-Equivalent Transistor Model
3.5.1 Threshold Voltage
3.5.2 Carrier Mobility
3.5.3 Oxide Breakdown
3.6 Aging Model for Hand Calculations
3.7 Conclusions
4 Background on IC Reliability Simulation
4.1 Introduction
4.2 Literature Overview
4.2.1 Berkeley Reliability Tools (BERT)
4.2.2 Other Reliability Simulators
4.3 Commercial Reliability Simulators
4.3.1 The Mentor Graphics Reliability Simulator
4.3.2 The Cadence Reliability Simulator (BERT/RelXpert)
4.3.3 The Synopsys Reliability Simulator (MOSRA)
4.4 Discussion
4.5 Conclusions
5 Analog IC Reliability Simulation
5.1 Introduction
5.2 Deterministic Reliability Simulation
5.2.1 Problem Statement
5.2.2 Implementation
5.2.3 Circuit Example
5.3 Stochastic Reliability Simulation
5.3.1 Problem Statement
5.3.2 Implementation 1: Monte-Carlo Simulation
5.3.3 Implementation 2: A Response Surface Methodology
5.3.4 Circuit Example
5.4 Hierarchical Reliability Simulation
5.4.1 Problem Statement
5.4.2 Implementation
5.4.3 Circuit Example
5.5 Conclusions
6 Integrated Circuit Reliability
6.1 Introduction
6.2 Assessment
6.2.1 Observed Performance Parameter
6.2.2 Process Capability Index
6.2.3 Technology
6.2.4 Circuit Design
6.2.5 Stress Conditions
6.3 Failure-Resilient Circuits
6.3.1 Intrinsically Robust Circuits
6.3.2 Self-healing Circuits
6.4 Case Study 1: IDAC
6.4.1 Technology
6.4.2 Conventional Design
6.4.3 Reliability-Aware Design: Fixed Topology
6.4.4 Reliability-Aware Design: Digitally-Assisted Analog
6.5 Case Study 2: Digital Circuits
6.5.1 Digital Circuit Lifetime
6.5.2 Minimum Circuit Lifetime
6.5.3 Example Circuit
6.6 Conclusions
7 Conclusions
7.1 General Conclusions
7.2 Major Contributions
7.3 Suggestions for Improvements and Future Work
List of Publications and Biography
ISBN: 978-94-6018-578-6
Publication status: published
KU Leuven publication type: TH
Appears in Collections:Electrical Engineering - miscellaneous
ESAT - MICAS, Microelectronics and Sensors

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