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Title: Design, Fabrication and Characterization of Tunnel Field Effect Transistors for Ultra-Low Power CMOS Applications (Ontwerp, fabricatie en karakterisatie van tunnel veld effect transistoren voor ultra-laag vermogen CMOS toepassingen)
Other Titles: Design, Fabrication and Characterization of Tunnel Field Effect Transistors for Ultra-Low Power CMOS Applications
Authors: Leonelli, Daniele; S0197777;
Issue Date: 1-Oct-2012
Abstract: Silicon CMOS has emerged over the last 25 years as the predominant technology of the microelectronics industry. The concept of device scaling has been consistently applied over many technology generations, resulting in consistent improvement in both device density and performance. In the last decade, the shrinking of the transistor dimensions led to short channel effects (SCEs) which decreases the device performance. As a consequence, additional improvements were needed to maintain the performance improvements such as the introduction of SiGe S/D stressors to increase the carrier mobility due to the strain in the channel, the implementation of high-K and metal gate to reduce the gate leakage and, finally, the introduction of a new 3D architecture, finFET, to further suppress the SCEs. On the other hand, no solutions exist for the scaling of the dissipated power of the transistor. In fact, the scaling of the supply voltage (Vdd) is limited by the kT/q limit of the subthreshold slope which represents a physical limit for conventional MOSFETs. As a consequence, a new operation principle is needed.In this context, the Tunnel FET (TFET) has been proposed as a potential candidate to replace the MOSFET because its carrier injection mechanism based on quantum mechanical tunneling of the electrons from valence band to the conduction band and it is not subjected to the kT/q limit. The basic embodiment of TFET is a gated p-i-n diode. This thesis addresses the design, fabrication and characterization of TFETs following a CMOS compatible processing flow. The main goal is to understand the features of band to band tunneling from an experimental point of view and identify the best processing conditions and the best architecture for TFETs. The analysis starts from silicon homojunction gated p-i-n diodes to heterojunction devices where the source is replaced with SiGe with different germanium concentrations. Two different architectures are studied: finFETs and vertical nanowires. The finFETs are used as a test vehicle to study Si TFETs since the finFET processing is already mature. On the other hand, the vertical architecture is used to implement hetero junction TFET. Finally, in view of the limitations for the basic TFET embodiments, a new architecture to boost the on current of TFETs is proposed and analyzed by TCAD simulations.
Table of Contents: CHAPTER 1: Introduction
1.1 MOSFET SCALING ISSUES
1.2 POWER CRISIS
1.3 THE QUEST FOR AN ENERGY-EFFICIENT SWITCH
1.4 THE TFET: FROM CONCEPT TO DEVICE
1.5 RESEARCH OBJECTIVE AND DISSERTATION OUTLINE

CHAPTER 2: Physical Theories
2.1 INTRODUCTION
2.2 BAND-TO-BAND TUNNELING
2.2.1 The Kane’s Model and its Limitations
2.2.2 Tunneling Probability and Imaginary Wave Vector
2.2.3 Concept of Effective Bandgap
2.3 LEAKAGE MECHANISMS IN TFET
2.3.1 Theory of an Ideal Diode
2.3.2 SRH Component
2.3.3 Trap-Assisted Tunneling (TAT)
2.3.4 Arrhenius Plot
2.4 TCAD SIMULATION OF TFETS
2.4.1 Introduction
2.4.2 BTBT in Sentaurus Synopsys
2.4.3 Calibration of BTBT Models
2.5 LINE AND POINT TUNNELING
2.6 SUMMARY

CHAPTER 3: Fabrication of TFETs
3.1 INTRODUCTION
3.2 FINFET INTEGRATION OF TFET
3.2.1 Design of TFETs for Planar Integration
3.2.2 Fabrication of TFET for Planar Integration
3.3 INTEGRATION OF VERTICAL NANOWIRE-BASED TFET
3.3.1 Design of vertical TFET
3.3.2 Fabrication of homojunction TFET
3.3.3 Fabrication of heterojunction TFET
3.4 SUMMARY

CHAPTER 4: Basic Characterization of TFETs
4.1 INTRODUCTION
4.2 METHODS OF CHARACTERIZATION OF TFET
4.2.1 Electrical Characterization Tools
4.2.2 Methodologies and Parameters Extraction
4.3 TUNNEL FIELD EFFECT TRANSISTOR (TFET)
4.3.1 Transfer Characteristics
4.3.2 Output Characteristics
4.3.3 The subthreshold swing in TFET
4.3.4 How to Identify Band to Band Tunneling
4.4 SUMMARY

CHAPTER 5: FinFET-based Si TFETs
5.1 TFET AT IMEC
5.2 IMPACT OF FIN WIDTH IN TFETS
5.2.1 Gate Geometry and Electrostatic Integrity
5.2.2 Impact of Gate Geometry on TFET
5.3 OXIDE SCALING AND TFET PERFORMANCE
5.4 TUNNELING JUNCTION ENGINEERING THROUGH DOPING
5.5 IMPACT OF THE ANNEALING CONDITIONS
5.5.1 The Trend in MOSFET
5.5.2 The Trend in TFET
5.6 SILICIDE ENGINEERING BY DOPANT SEGREGATION
5.6.1 SB TFET
5.6.2 Dopant-Segregated (DS) Schottky TFET
5.7 PERFORMANCE OF TFET
5.8 SUMMARY

CHAPTER 6: Vertical Nanowire-based TFETs for Heterojunction
Integration
6.1 INTRODUCTION
6.2 VERTICAL-BASED SI TFET
6.2.1 Impact of the Nanowire Diameter
6.2.2 Impact of the Gate-Source & Gate-Drain overlaps
6.3 HETEROJUNCTION VERTICAL NTFET
6.3.1 Introduction
6.3.2 Impact of the Ge Concentration and δ-layer
6.3.3 Impact of the Si Capping Layer
6.4 ANALYSIS OF THE TFET PERFORMANCE
6.4.1 Extraction of Interface Traps
6.4.2 Temperature Dependence
6.5 SUMMARY

CHAPTER 7: Hybrid TFETs - a New Architecture
7.1 INTRODUCTION
7.2 THE LIMITATIONS OF THE LATERAL TFET
7.3 THE HYBRID TFET
7.3.1 Impact of Geometrical Parameters
7.3.2 Optimization of the Hybrid TFET
7.3.3 The Fabrication of the Hybrid TFET
7.4 SUMMARY

CHAPTER 8: Conclusions, Future Work and Outlook
8.1 GENERAL CONCLUSIONS
8.2 FUTURE WORK AND OUTLOOK

APPENDIX: Physical Characterization Methods
LIST OF PUBLICATIONS
ISBN: 978-94-6018-540-3
Publication status: published
KU Leuven publication type: TH
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors

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