A Programmable Calibration/BIST Engine for RF/Analog Blocks in SoCs
Hermosillo, Jorge Carballido, Jorge Veloz, Arturo Arditti, David Del Rio, Alberto Borrayo, Edgar Guzmann, Manuel Lakdawala, Hasnain Verhelst, Marian #
European Solid State Circuits Conference location:Bordeaux date:September 2012
A programmable digital engine for RF/analog on-/off-line calibration and Built-in Self-Test (BIST) enables a new level of robustness and portability for mixed signal SoCs. The drop-in IP-block is based on a dedicated CPU with data path and instruction set extensions optimized for the compute intensive RF calibration algorithms. The concept is
demonstrated with an implementation in a 32nm SoC test chip
where the 0.63mm2 engine has been fully integrated with a WiFi radio and has been used to measure and calibrate its inherent non-idealities and to evaluate its performance.