Title: Device performance of transistors with high-kappa dielectrics using cross-wafer-scaled interface-layer thickness
Authors: O'Sullivan, B.J. ×
Kaushik, V.S.
Ragnarsson, L.A.
Onsia, B.
Van Hoornick, N.
Rohr, E.
De Gendt, Stefan
Heyns, Marc #
Issue Date: Jan-2006
Publisher: Ieee-inst electrical electronics engineers inc
Series Title: IEEE Electron Device Letters vol:27 issue:7 pages:546-548
Abstract: A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO2 interface layer between a silicon substrate and high-kappa, dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO2 interface. This technique provides a,powerful tool in examining the effect of the process variations on device performance.
ISSN: 0741-3106
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Molecular Design and Synthesis
Department of Materials Engineering - miscellaneous
× corresponding author
# (joint) last author

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