We report on gate patterning development for the 45 nm node and beyond. Both poly-Si and different metal gates in combination with medium-k and high-k dielectrics have been defined. Source/drain silicon recess has been characterized for different stacks, yielding optimised processes for all investigated. Using hardmask based etching allowed us to produce sub-20 nm poly-Si and metal gates. Implementation of advanced metal gate patterning in already developed multigate field effect transistors (MuGFET) devices has been demonstrated. (c) 2004 Elsevier Ltd. All rights reserved.