Title: Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance
Authors: Mercha, A
Van der Plas, G
Moroz, V
De Wolf, Ingrid
Asimakopoulos, Panagiotis
Minas, N
Domae, S
Perry, D
Choi, M
Redolfi, A
Okoro, Chukwudi
Yang, Y
Van Olmen, J
Thangaraju, S
Tezcan, D. Sabuncuoglu
Soussan, P
Cho, J. H
Yakovlev, A
Marchal, P
Travaly, Y
Beyne, E
Biesemans, Samuel
Swinnen, B #
Issue Date: 2010
Publisher: Ieee
Host Document: 2010 international electron devices meeting - technical digest pages:-
Series Title: International Electron Devices Meeting
Conference: International Electron Devices Meeting (IEDM) San Francisco, CA, DEC 06-08, 2010
Abstract: As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.
ISBN: 978-1-4244-7419-6
Publication status: published
KU Leuven publication type: IC
Appears in Collections:Department of Materials Engineering - miscellaneous
Production Engineering, Machine Design and Automation (PMA) Section
# (joint) last author

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