Gate Voltage Influence on the Channel Hot-Carrier Degradation of High-k-Based Devices
Amat, Esteve × Kauerauf, Thomas Degraeve, Robin Rodriguez, Rosana Nafria, Montserrat Aymerich, Xavier Groeseneken, Guido #
Institute of Electrical and Electronics Engineers
IEEE Transactions on Device and Materials Reliability vol:11 issue:1 pages:92-97
In ultrascaled complimentary metal-oxide-semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high-k). A new model to describe the CHC degradation behavior in n-channel metal-oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high-k or SiO2 as a dielectric.