Title: Design issues and considerations for low-cost 3-D TSV IC technology
Authors: Van der Plas, Geert ×
Limaye, Paresh
Loi, Igor
Mercha, Abdelkarim
Oprins, Herman
Torregiani, Cristina
Thijs, Steven
Linten, Dimitri
Stucchi, Michele
Katti, Guruprasad
Velenis, Dimitrios
Cherman, Vladimir
Vandevelde, Bart
Simons, Veerle
De Wolf, Ingrid
Labie, Riet
Perry, Dan
Bronckers, Stephane
Minas, Nikolaos
Cupac, Miro
Ruythooren, Wouter
Van Olmen, Jan
Phommahaxay, Alain
de ten Broeck, Muriel de Potter
Opdebeeck, Ann
Rakowski, Michal
De Wachter, Bart
Dehan, Morin
Nelis, Marc
Agarwal, Rahul
Pullini, Antonio
Angiolini, Federico
Benini, Luca
Dehaene, Wim
Travaly, Youssef
Beyne, Eric
Marchal, Paul #
Issue Date: Jan-2011
Publisher: Institute of Electrical and Electronics Engineers
Series Title: IEEE Journal of Solid-State Circuits vol:46 issue:1 pages:293-307
Conference: International Solid-State Circuits Conference (ISSCC) San Francisco, CA, Feb. 07-11, 2010
Abstract: In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes Vth shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 mm(2)) and power (3%) overhead.
ISSN: 0018-9200
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Department of Materials Engineering - miscellaneous
Associated Section of ESAT - INSYS, Integrated Systems
ESAT - MICAS, Microelectronics and Sensors
× corresponding author
# (joint) last author

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