Materials and Technologies for 3-D Integration, Date: 2008/12/01 - 2008/12/03, Location: Boston, MA USA
Publication date:
2009-01-01
Volume:
1112
Pages:
159 -
164
ISSN:
978-1-60511-084-4
Publisher:
Materials research society
Materials and Technologies for 3-D Integration
Author:
Radisic, Alex
Luhn, Ole ; Swinnen, Bart ; Bender, Hugo ; Drijbooms, Chris ; Doumen, Geert ; Kellens, Kristof ; Ruythooren, Wouter ; Vereecken, Philippe
Keywords:
Science & Technology, Technology, Engineering, Electrical & Electronic, Materials Science, Multidisciplinary, Engineering, Materials Science, COPPER, MODEL
Abstract:
In this paper we report on Cu plating of through-Silicon-vias (TSV-s) with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits (3D-SIC). © 2009 Materials Research Society.