Dielectrics for Nanosystems 4: Materials Science, Processing, Reliability, and Manufacturing, Date: 2010/04/25 - 2010/04/25, Location: Vancouver Canada
Dielectrics for Nanosystems 4: Materials Science, Processing, Reliability, and Manufacturing
Author:
Keywords:
Science & Technology, Physical Sciences, Electrochemistry, Nanoscience & Nanotechnology, Science & Technology - Other Topics, EPITAXIAL-GROWTH, SI, PERFORMANCE, GERMANIUM, 4008 Electrical engineering, 4017 Mechanical engineering, 4018 Nanotechnology
Abstract:
Recently, best 65 nm Ge pMOSFET performance has been reported with a standard Si CMOS HfO2 gate stack module (1). In this contribution, we investigated in more detail how device performance, especially the hole mobility, depends on the characteristics of layers featuring the gate dielectric (HfO2, SiO2 and the Si cap layer). We found that many point defects are involved in the mobility control. We specifically highlight the role of defects linked to the Si cap integration. A critical Si thickness is also extracted, separating two important regimes. We finally report the difference in hole-mobility-limiting mechanisms between Ge devices integrating two different Epi-Si passivation schemes. Based on low temperature measurements, the promising Si3H8 process shows an additional coulomb scattering mechanism compared to SiH4. ©The Electrochemical Society.