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ISSCC, Date: 2010/02/08 - 2010/02/11, Location: San Francisco, CA, USA

Publication date: 2010-01-01
Volume: 53 Pages: 148 - 149
ISSN: 9781424460342
Publisher: IEEE

IEEE International Solid-State Circuits Conference - ISSCC

Author:

Van de Plas, G
Limaye, P ; Mercha, A ; Oprins, H ; Torregiani, C ; Thijs, S ; Linten, D ; Stucchi, D ; Cherman, V ; Vandevelde, B ; Simons, V ; De Wolf, Ingrid ; Labie, R ; Perry, D ; et al,

Keywords:

TSV, design

Abstract:

3D TSV (through silicon via) technologies promise increased system integration at lower cost and reduced footprint. Different variants of 3D technologies have recently been introduced in application areas such as DRAM stacking, imagers, SSDs (Solid-StateDrives). In this paper we investigate the design issues and solutions of a low cost 3D TSV Stacked-IC technology. This technology offers a 10 μm TSV pitch that enables applications such as logic onlogic, DRAM-on-logic and RF-on-logic. We present experimental data on key issues such as impact of TSV on MOS devices and back-end-of-line (BEOL), reliability, thermal hot spots, ESD, signal integrity and circuit performance. Furthermore, we point out where changes in current design practices are required to realize the low-cost potential of the technology.