Title: Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures
Authors: Yang, Yu ×
Labie, Riet
Ling, Fangzhou
Zhao, C
Radisic, A
Van Olmen, J
Travaly, Y
Verlinden, Bert
De Wolf, Ingrid #
Issue Date: Sep-2010
Publisher: Pergamon-elsevier science ltd
Series Title: Microelectronics reliability vol:50 issue:9-11 pages:1636-1640
Conference: ESREF edition:2010 location:Gaeta, Italy date:Oct 2010
Abstract: Through-silicon vias (TSVs) are critical components in most 3D architectures. In this paper, fully filled cylindrical Cu TSVs with a diameter of 5 mu m and a depth of 25 mu m were used to demonstrate quantitative assessment of the fabrication process and the interfacial adhesion of the TSVs. For TSV fabrication, the coverage of barrier and seed layers was respectively examined through dilute HF dipping and copper decoration plating. The adhesion between the TSVs and the substrate, which is of great importance for the functionality and long-term reliability of the TSVs, was characterized by four-point bending in combination with fractographic analysis. The scanning electron microscopic (SEM) images of the fracture indicate that the top of a TSV has better adhesion than the rest. This can be due to the non-uniformity of sidewall roughness and barrier thickness. A degradation of adhesion at the top was observed after thermal cycling tests, which seems to confirm the hypothesis of the influence of the roughness. These reliability tests should be taken as additional criteria for the assessment of TSV properties. (C) 2010 Elsevier Ltd. All rights reserved.
ISSN: 0026-2714
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Physical Metallurgy and Materials Engineering Section (-)
Department of Materials Engineering - miscellaneous
Chemical and Extractive Metallurgy Section (-)
× corresponding author
# (joint) last author

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