IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol:29 issue:12 pages:1884-1893
This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits.
First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator.
Next, a method to analyse the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy trade-off with a nearly-linear complexity for all circuits under test.
Finally, based on the DoE-analysis, a circuit response surface model (RSM) is derived.
The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime.
The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to 3 orders of magnitude, when compared to standard Monte-Carlo based techniques and while still maintaining simulation accuracy.