Title: Circuit Design for Bias Compatibility in Novel FinFET based floating RAM
Authors: Poliakov, Pavel ×
Anchlia, A.
Garia Bardon, M.
Rooseleer, Bram
De Wachter, B.
Collaert, N.
van der Zanden, K.
Dehaene, Wim
Verkest, D.
Corbalan, Miranda #
Issue Date: Mar-2010
Publisher: Institute of Electrical and Electronics Engineers
Series Title: IEEE Transactions on Circuits and Systems II, Express Briefs vol:57 pages:183-187
ISSN: 1549-7747
Publication status: published
KU Leuven publication type: IT
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors
Associated Section of ESAT - INSYS, Integrated Systems
× corresponding author
# (joint) last author

Files in This Item:

There are no files associated with this item.

Request a copy


All items in Lirias are protected by copyright, with all rights reserved.

© Web of science