Reliability of Strained-Si Devices With Post-Oxide-Deposition Strain Introduction
Shickova, Adelina × Verheyen, Peter Eneman, Geert Degraeve, Robin Simoen, Eddy Favia, Paola Klenov, Dmitri O San Andres, Enrique Kaczer, Ben Jurczak, Malgorzata Absil, Philippe Maes, Herman E Groeseneken, Guido #
Ieee-inst electrical electronics engineers inc
Ieee transactions on electron devices vol:55 issue:12 pages:3432-3441
To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa. and FUSI/high-kappa, gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.