Title: High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants
Authors: Hellings, Geert ×
Mitard, Jerome
Eneman, Geert
De Jaeger, Brice
Brunco, David P
Shamiryan, Denis
Vandeweyer, Tom
Meuris, Marc
Heyns, Marc M
De Meyer, Kristin #
Issue Date: Jan-2009
Publisher: Ieee-inst electrical electronics engineers inc
Series Title: IEEE Electron Device Letters vol:30 issue:1 pages:88-90
Abstract: Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2, resulting in a significant I-ON boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for I-ON by 50%, maintaining similar I-OFF, as measured at the source.
ISSN: 0741-3106
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Associated Section of ESAT - INSYS, Integrated Systems
ESAT - MICAS, Microelectronics and Sensors
× corresponding author
# (joint) last author

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