Title: The impact of back-side Cu contamination on 3D stacking architecture
Authors: Yang, Yu ×
Labie, Riet
Richard, Olivier
Bender, Hugo
Zhao, Chao
Verlinden, Bert
De Wolf, Ingrid #
Issue Date: 2010
Publisher: Electrochemical soc inc
Series Title: Electrochemical and solid state letters vol:13 issue:2 pages:H39-H41
Abstract: Three-dimensional (3D)-stacked Si chip architecture using Cu through-silicon vias can make microelectronic devices vulnerable to Cu contamination. In this article, 130 nm complementary metal oxide semiconductor devices were used to investigate back-side Cu contamination. Cu was deposited directly on the back side of thin wafers, which were further annealed at 350 degrees C. No prominent degradation was observed for key device parameters. A multilayer of Cu/SiO2 (400 nm)/Si was revealed by focused ion beam-scanning electron microscopy, and transmission electron microscopy. X-ray diffraction was conducted on a blank wafer to study the interaction between Cu and Si. The exceptional growth of silicon oxide at room temperature is explained by a partial reconstitution mechanism of the catalytic Cu3Si. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3269603] All rights reserved.
ISSN: 1099-0062
Publication status: published
KU Leuven publication type: IT
Appears in Collections:Physical Metallurgy and Materials Engineering Section (-)
Department of Materials Engineering - miscellaneous
× corresponding author
# (joint) last author

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