Title: Design and synthesis of pareto buffers offering large range runtime energy/delay tradeoffs via combined buffer size and supply voltage tuning
Authors: Wang, H. ×
Miranda, M.
Dehaene, Wim
Catthoor, Francky #
Issue Date: Jan-2009
Publisher: Institute of Electrical and Electronics Engineers
Series Title: IEEE transactions on very large scale integration (VLSI) systems vol:17 issue:1 pages:117-127
ISSN: 1063-8210
Publication status: published
KU Leuven publication type: IT
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors
Associated Section of ESAT - INSYS, Integrated Systems
× corresponding author
# (joint) last author

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