Analog integrated circuits and signal processing vol:55 issue:1 pages:37-45
This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 mu m CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.