Analog integrated circuits and signal processing vol:55 issue:1 pages:85-91
The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13 mu m CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors of the level shifter operate within the voltage limits imposed by the design rules of a mainstream CMOS technology.