Digest of the 4th Workshop on Optimization for DSP and Embedded Systems (ODES-4) pages:1-10
Workshop on Optimization for DSP and Embedded Systems edition:4 location:New York, New York date:March 2006
Current emerging embedded System-on-Chip platforms are increasingly
becoming multiprocessor architectures. System designers
experience significant difficulties in programming these platforms.
The applications are typically specified as sequential programs
that do not reveal the available parallelism in an application,
the efficient mapping of an application onto a
parallel multiprocessor platform.
In this paper we present our compiler techniques that facilitate
the migration from a sequential application specification
to a parallel application specification using the Process Network
model of computation. Our work is inspired by a previous research
project called Compaan. With our techniques we address
optimization issues such as the generation of Process Networks with
simplified topology and communication
without sacrificing the Process Networks performance.
Moreover, we describe a technique for compile-time
memory requirement estimation
which we consider as an important contribution of this paper. We demonstrate
the usefulness of our techniques on several examples.