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Title: Methodology for building processor design space exploration frameworks
Authors: Barat, F
Vander Aa, Tom
Jayapala, Murali
Deconinck, Geert
Lauwereins, Rudy
Corporaal, H #
Issue Date: 2005
Host Document: Proceedings of 3rd Workshop on optimizations for DSP and embedded systems (ODES-3) pages:10
Conference: 3rd Workshop on optimizations for DSP and embedded systems (ODES-3) location:San José, Ca, USA date:March 20, 2005
Description: Proceedings of 3rd Workshop on optimizations for DSP and embedded systems (ODES-3)
URI: 
Publication status: published
KU Leuven publication type: IC
Appears in Collections:ESAT - ELECTA, Electrical Energy Computer Architectures
Associated Section of ESAT - INSYS, Integrated Systems
# (joint) last author

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