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Title: A 15-b resolution 2-MHz Nyquist rate sigma-delta ADC in a 1-um CMOS technology
Authors: Marques, Augusto
Peluso, Vincenzo
Steyaert, Michel
Sansen, Willy #
Issue Date: Jul-1998
Publisher: Ieee-inst electrical electronics engineers inc
Series Title: IEEE Journal on Solid-State Circuits vol:33 issue:7 pages:1065-1075
Abstract: A high-resolution high-speed fourth-order cascaded Delta Sigma analog-to-digital converter, based on a 2-1-1 topology, is presented, The converter is implemented with fully differential switched capacitor circuits in a standard 1-mu m CMOS technology, The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage.
URI: 
ISSN: 0018-9200
Publication status: published
KU Leuven publication type: IT
Appears in Collections:ESAT - MICAS, Microelectronics and Sensors
Electrical Engineering - miscellaneous
# (joint) last author

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