Medium Frequency Physical Vapor Deposited Al 2 O 3 and SiO 2 as Etch-Stop-Layers for Amorphous Indium-Gallium-Zinc-Oxide Thin-Film-Transistors

In this work, we report on amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-ﬁlm transistor (TFT) with medium frequency physical vapor deposited (mf-PVD) etch-stop-layer (ESL). TFT with mf-PVD ESL show comparable characteristics such as ﬁeld-effect mobility ( μ FE ), sub-threshold slope (SS − 1 ) and current ratio (I ON/OFF ) to the conventional plasma enhanced chemical vapor deposition (PECVD) ESL based TFT, however signiﬁcant differences were observed in gate bias-stress stabilities. The TFTs with mf-PVD ESL showed lower threshold-voltage (V TH ) shifts compared to TFTs with PECVD ESL when stressed under a gate ﬁeld of + / − 1 MV/cm for duration of 10 4 seconds in dark and light conditions. We associate the better bias-stress stability of the mf-PVD ESL based TFT to better passivating properties and the low hydrogen content of the mf-PVD layer compared to PECVD layer. © The

Amorphous oxide semiconductors (AOSs) are gaining traction to replace the a:SiH in TFTs applied in liquid crystal display (LCD) and organic light-emitting diode display (OLED) backplanes. These oxide semiconductor have high transparency and relatively high electron mobility in the amorphous state. An additional advantage lies in the low process temperature required for AOS integration on plastic film and so potentially enabling flexible transparent display and electronics. Among many AOSs, a-IGZO is the most promising due to its high mobility, excellent uniformity, and the compatibility with transparent and flexible substrate, as compared to conventional amorphous and polycrystalline silicon. [1][2][3][4][5][6][7][8] For either LCD or OLED displays with IGZO backplane, bottom-gate top-contact (BGTC) ESL configuration is preferred. The ESL protects the a-IGZO back channel from damages caused during the source-drain metallization and patterning. [9][10][11] The damage-free surface improves the bias stabilities especially at accelerated bias stress conditions under illumination. However commonly the ESL is deposited by plasma assisted CVD processes to which a-IGZO can be sensitive. 12 Therefore there is a need to investigate the effect of the ESL on the characteristics of a-IGZO TFTs.
PECVD based SiO 2 deposited at temperature higher than 350 • C using SiH 4 /N 2 O chemistry is commonly used as an ESL in Flat-Panel-Display (FPD) industry due to its fast deposition rate, high uniformity and good step coverage. For the integration on commercialized flexible substrates like PEN or polyimide, deposition and process temperature should be lower to prevent shrinkage of the plastic foil and allow easy de-lamination. It is known that PECVD layer deposited at lower temperature deteriorate layer quality leading to lower density, higher amount of dangling bonds and an increase in the amount of hydrogen incorporated into the SiO 2 layer. The poor density and increase of hydrogen is problematic for a-IGZO TFTs because it leads to uncontrolled doping density. [13][14] Few research groups have demonstrated the use of PVD based dielectrics (SiO 2 and Al 2 O 3 ) as passivation layer or ESL as an alternative to PECVD layer which has the doping issue with a-IGZO. 15,16,22 Despite the fact that PVD dielectrics intrinsically contain less hydrogen, parameters such as deposition rates, uniformity, defect density and electrical properties like leakage current and breakdown voltage are often insufficient to meet the manufacturing requirements of the industry. Recently mf-PVD Al 2 O 3 layers have been demonstrated with high deposition rate and sufficient uniformity up to Gen-8 size. 17 This might allow to replace the conventional PECVD SiO 2 layer to achieve better TFT characteristics. In this paper, we z E-mail: manoj.nag@imec.be realized IGZO-TFTs with different mf-PVD ESL (SiO 2 and Al 2 O 3 ) and compared them to conventional PECVD SiO 2 ESL based TFTs.

Experimental
All TFT were made on conducting silicon substrate with thermal SiO 2 (120 nm) as gate dielectric and the Si substrate was used as a common gate electrode. The use of high-quality high-temperature thermal SiO 2 guarantees that none of the observed bias instabilities is related to the gate dielectric (GD) layer. In the first step, a-IGZO layer was deposited by dc sputtering at room temperature (RT) using a-IGZO target (In : Ga : Zn = 1 : 1 : 1 atomic%) using a Ar/ O 2 mixture. Following the a-IGZO deposition, three different kinds of etch-stoplayers of equal thickness were deposited on three different samples i.e. two layers were deposited by mf-PVD (50 kHz) of Si and Al at room temperature with Ar/O 2 mixture and one by PECVD at 200 • C with SiH 4 /N 2 O chemistry. In the next step the ESL/a-IGZO stack was patterned by dry etch and wet etch followed by contact opening by dry etch. The Mo S/D contacts were formed by molybdenum (Mo) sputtering and dry etch. All layers were patterned by standard photolithography. In the last step all the samples were subjected to thermal annealing at 250 • C in N 2 ambient for 1 hr. The electrical properties of a-IGZO TFTs were measured using an Agilent 4156 parameter analyzer in N 2 environment. The characteristics of the ESL were measured by the ellipsometry and electrical characterization techniques. Relative layer density was characterized with standard BHF (1:50 with H 2 O) wet etch rate and hydrogen % was characterized by Elastic-Recoil-Detection (ERD) technique.

Results and Discussion
The use of high quality thermally grown SiO 2 as gate-dielectric assures that any variations in TFT characteristics and the bias-stress stabilities are most likely related to the ESL. Fig. 1 shows a schematic cross-section of the a-IGZO TFTs. Fig. 2(a) and 2(b) shows typical transfer (I DS -V GS ) and output (I DS -V DS ) characteristics of three TFTs. As listed in Table I, for TFTs with mf-PVD ESLs the characteristics such as μ FE , SS −1 and I ON/OFF ratio are between 15-17 cm 2 /V.s, 0.20-0.30 V/decade and < 10 7 respectively. TFT with PECVD SiO 2 ESL in comparison has a substantially lower μ FE of 10-12 cm 2 /V.s; while the other parameters are comparable to the TFT with mf-PVD ESL.
In case of the PECVD based ESL, the impact of the deposition temperature on the TFT characteristics cannot be completely decoupled between the change in SiO 2 quality and the impact of the temperature on the a-IGZO. The low deposition temperature (<250 • C) of PECVD SiO 2 ESLs lead to increase in hydrogen content, decrease in the density and corresponding poorer electrical performance. Several research groups have reported that hydrogen atoms produced by SiH 4 plasma diffuse fast in the a-IGZO layer, creating a shallow electron donor level. 18 On the other hand, oxygen atoms in N 2 O plasma were inclined to oxidize the a-IGZO layer surface, which decreased the carrier concentration of a-IGZO layers. 19 An optimized H 2 and O 2 plasma ratio layer can lead to improved transistor characteristics. In case of mf-PVD layers, optimized sputter plasma (O 2 to Ar ratio) tends to cause less impact on the a-IGZO below. In this case, because no hydrogen source is present, changes in TFT characteristics related to hydrogen doping can be ruled out with exemption to the PECVD SiO 2 . The Ar rich plasma can change the a-IGZO layer from semiconducting to conducting by changing the ratio of metal atoms (Ga, In and Zn) and the O 2 rich plasma can cause the surface oxidation leading to more resistive layer and therefore both can influence the TFT characteristics. In fact it is reported that the Ar plasma treated surface has relatively higher In and relatively lower Ga and Zn due to the difference of the sputtering yield of these atoms. 20 However, these differences are reduced after an annealing step. In case of TFT with mf-PVD ESLs, high mobility and negative V TH could be due to the change in the conductivity of the channel at the ESL interface. It could also be possible that the longer or higher temperature anneal conditions are required for mf-PVD ESL based TFTs to have similar properties like PECVD ESL based TFT. In further TFT characterizations, i.e. the bias-stress stabilities in dark conditions as shown in  Table II. It is clearly understood that PECVD SiO 2 layer's based TFTs it is clear that the PECVD SiO 2 layer's hydrogen content is 6.43 at.% which is much higher than 1.01 at. % of mf-PVD SiO 2 layer and 2.8 at.% of mf-PVD Al 2 O 3 layer.
In bias stress experiments in the dark (NBS and PBS) and under light (NBIS) conditions, the change at back channel interface due to the ESL deposition dominate the V TH shift. Not much is reported on these stress stabilities for PVD ESL based TFTs. In few publications where PVD layer (SiO 2 and Al 2 O 3 ) is used as passivation layer [15][16] or as dopant blocking layer, 21 little explanation around the NBS and PBS is provided. In our previous work; we compared the mf-PVD SiO 2 ESL based TFT characteristics and their bias-stress stabilities (PBS and NBS) to high temperature (300 • C) PECVD SiO 2 and low temperature (200 • C) SiO 2 ESL based TFTs. 22 We observed that high temperature PECVD SiO 2 ESL and mf-PVD SiO 2 ESL based TFTs show comparable characteristics. Here we extended our work with the addition of mf-PVD Al 2 O 3 ESL TFT characteristics and their biasstress stabilities (NBS and PBS) data. In addition NBIS data for all the ESL stacks (PECVD SiO 2 , mf-PVD SiO 2 and mf-PVD Al 2 O 3 ) have been elaborated on. In PBS as the TFT operate in fully on mode, only the front interface (a-IGZO/gate dielectric) is important. However the positive V TH shift can be explained by assuming oxygen adsorption on the back surface of the active layer which decreases the concentration of free electrons in the channel layer. 23 A passivation layer (ESL in this case) which isolates the channel layer from the environment prevents oxygen adsorption effectively, and thus solves the problem. The 200 • C PECVD layer has extremely high etch rate as listed in Table II, this mean that the layer is poor in density; could have lots of pin holes and thus poor for the passivation for O 2 and water. So oxygen adsorptions at the back interface resulted to large positive shifts. In NBS, the TFT works in depletion mode both the interfaces (a-IGZO/thermal SiO 2 and a-IGZO/ESL) are active, however the impact of the front interface (a-IGZO/thermal SiO 2 ) will be much lower or negligible and also similar to PVD ESL case. So on a similar note as in the PBS case the back interface change dominates the shift in NBS as well, the external humidity and other gas molecules can thus permeate through these empty regions of poor passivation. Moisture reaching the a-IGZO layer enhances the generation of shallow donor states created by visible light radiation and thus induces an increase in carrier density within a-IGZO. This enhances the conductivity and so reflects in large negative shifts under bias conditions. Other possible explanation is the peak hydrogen concentration which varies opposite to deposition temperature in PECVD processes i.e. layers at 200 • C will contains higher hydrogen than that of layers athigher temperature. These results support the conjecture that a significant amount of hydrogen must have been incorporated for low temperature layers case. Hydrogen is well known to contribute shallow donor states to a-IGZO, which increases their electrical conductivity. It is very probable that the incorporation of hydrogen has generated donor states within the a-IGZO bulk, hence inducing a large -ve shift due to the additional carriers. Over all in both the PBS and the NBS cases, the difference in the amount of the V TH shift originate from the difference in bond structure at the a-IGZO/ESL interface. The deposition temperature of SiO 2 has a strong influence on both the microstructure of SiO 2 and the a-IGZO/SiO 2 interface bonding state. The silicon oxide layer when deposited at a higher temperature (>300 • C) much stronger bonds could be formed at the interface. 22,24 The quality of the a-IGZO/SiO 2 interface is conjectured to determine the V TH shift of all TFTs in bias tests. Reported higher temperature (deposited >300 • C) PECVD ESLs or passivation and dual layer passivation layers stacks due to their much better passivating properties do not show similar kind of large PBS and NBS shifts. [25][26] Quite similar to NBS explanation, the back channel interface change produces a substantial instability under NBIS. It is reported that the back channel interface exhibits a high-density of near valence-band-maximum (VBM) states caused by oxygen vacancies (V O ), which generate holes by photo-exciting electrons to the conduction band when illuminated. [27][28] The holes then diffuse to the interface of the gate dielectric by the assistance of the negative bias stress. Post a-IGZO process integration steps affect these back channel interface VBM states. ESL and passivation layers are used to prevent these back surface changes, however, the deposition conditions of those layers also impact the VBM states. The amount of oxygen, hydrogen and water molecules, which are present in these layers, become very important. It is also mentioned that increasing the amount of incorporated hydrogen (occurring during PECVD ESL deposition) increases the NBIS related instability due to formation of a hydrogen-related complex 29-30 and incorporated O 2 (possible in case of PVD ESL) in a-IGZO reduces the deep traps caused due to oxygen vacancy related defects. 31 In summary, PVD SiO 2 is deposited in oxygen rich plasma and this reduces the deep trap states close to the back surface. PECVD SiO 2 doesn't oxidize a-IGZO, but introduces interstitial hydrogen into the material which doesn't reduce the deep trap states and involve in large V TH shifts. To counter this some groups established N 2 O plasma treatment to back a-IGZO surface prior to PECVD SiO 2 deposition. This treatment oxidizes the top surface of the IGZO and reduces the diffusion of H 2 in the following SiH 4 gas step. The result of back interface change in case of N 2 O plasma is very much similar in PVD ESL deposition case. 24,26 We also extracted the traps for all the three different type of TFTs with NBIS data from the equation: where V TH is voltage shift under NBIS, K SiO = 3.9 for SiO 2 , K o = 8.854e −12 F/m, X ox is the thickness of dielectric. With the assumption of uniform distribution Q42 ECS Journal of Solid State Science and Technology, 4 (5) Q38-Q42 (2015) the above calculated charges were divided by thickness of a-IGZO. It is observed that the numbers for the PECVD SiO 2 layer's TFTs were much higher i.e. 1.5 e 18 cm −3 than in case of PVD layer case TFTs i.e. 4.50 e 17 cm −3 in PVD SiO 2 TFTs and 3.00 e 17 cm −3 in PVD Al 2 O 3 TFTs. Overall the lower hydrogen content of mf-PVD layer and its better passivating properties could be the reasons behind better biasstress stabilities of mf-PVD ESL based TFTs but parameters such as layer's density, dielectric constant and leakage, which correspond to the number of defects and the dangling bonds, can also influence the TFT characteristics. Further if we assumed that increased trapping due to higher defect density of the ESL would be the main issue, the improvement in bias-stress stability with PVD ESL should mostly be visible in the negative bias-stress and not significantly influence the positive bias-stress. As we see improvement in both positive and negative bias-stress stability (under dark), which is more in-line with changes in the bulk properties of a-IGZO with mf-PVD layer as ESL.

Conclusions
In summary, mf-PVD SiO 2 and mf-PVD Al 2 O 3 ESL based a-IGZO TFTs has been realized. In comparison to the conventional PECVD SiO 2 ESL based TFTs, the TFTs with mf-PVD (SiO 2 and Al 2 O 3 ) ESL exhibited better bias-stress stabilities under dark and light conditions. Better passivation properties and the lower hydrogen content of mf-PVD (SiO 2 and Al 2 O 3 ) layers has been identified as the major cause of this difference.