Author:

Keywords:

Science & Technology, Physical Sciences, Technology, Electrochemistry, Energy & Fuels, METAL IMPURITIES, DISLOCATIONS, DEFECTS, DLTS, 4008 Electrical engineering, 4017 Mechanical engineering, 4018 Nanotechnology

Abstract:

Impurity decoration of grain boundaries (GB) introduces deep levels and enhances their recombination activity. In this study we use the standard DLTS technique to investigate the influence of the GB structure on the electrical properties of mc-Si. The detected DLTS spectra have an opposite signal compared to the usually known majority carrier peaks of deep levels, but standard DLTS analysis can yield trap energies and capture cross sections. By comparing the properties between GB and intra-grain regions with similar minority carrier lifetime, it is considered that the DLTS signals might be due to traps generated in the extended defects present both at GBs and grains. It is observed that Σ3 GB has deep level traps at the same energy level as Σ9 GB, while the trap concentration in the former one is lower than the latter. Furthermore, a phosphorous gettering treatment can reduce the recombination activities both in the grains and at the GBs. ©The Electrochemical Society.