Author:

Abstract:

With the increasing demand for high-density, low-cost, high-speed and low-power nonvolatile memory (NVM) applications, alternative technologies, such as Phase Change RAM (PCRAM), Resistive RAM (RRAM), Spin-Transfer Torque Magnetic RAM (STT-MRAM) have been widely studied. Among them, RRAM attracts lots of attention, due to its excellent scaling potential below 10nm, low power operation, fast Program/Erase speed, etc. Furthermore, a simple two-terminal device structure allows implementation of RRAM in dense cross-point arrays, achieving the smallest cell footprint (4F2, with F being the technology feature size i.e. the half-metal pitch in memory technology). However, implementing resistive memory into high-density cross-point arrays has been hampered due to the (nearly) linear current-voltage (IV) characteristics of the resistive memory element. The leakage currents through the unselected resistive memory cells degrade the accessibility to a specific device in the array, causing write failure. During read operations, additional leakage currents reduce read sensing margin – the detectable difference between a high and low resistance states of the resistive memory element. Moreover, the wasteful parasitic currents raise power consumption to unacceptable levels. To solve these issues, introducing a separate two-terminal, non-linear selector device that is serially connected with each resistive memory element in a one-selector one-resistor (1S1R) configuration has been proposed as an effective way to introduce self-selectivity to the cross-point arrays. The parasitic leakage paths are suppressed due to the highly non-linear selector characteristics. This Ph.D. study focuses on the selector element for the one-selector one-resistor (1S1R) based cross-point arrays type RRAM. The performance requirements for implementing the selector device are derived from a memory array performance perspective, by employing a hybrid circuit simulation and an analytical analysis approach. Using the extrapolated selector design margin as guidance, different recent selector concepts are evaluated. The promising Metal-Silicon-Metal (MSM) selector is chosen for an in-depth experimental study to understand its performance, reliability, and the impact of selector variability on the overall 1S1R arrays performance. Finally, the selector requirements for vertical and stacked 3D cross-point array configurations are compared.